The present invention relates generally to electrically conductive interconnects, and more specifically, to an electrically conductive interconnect having an increased contact surface area.
Semiconductor devices can include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure are typically formed from copper (Cu) since copper-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum-based interconnects.
Within a typical dual damascene interconnect structure, for example, metal vias run perpendicular to the semiconductor substrate (e.g., the substrate thickness) and metal lines run parallel to the semiconductor substrate (e.g., the substrate length). Typically, the metal vias are present beneath the metal lines and both features are embedded within a dielectric material. Although various methods of forming such dual damascene interconnect structures are known, further improvements are needed to provide interconnect structures that provide greater speeds due to lower resistance, and are highly reliable.